DBGSTOP_IWDT=0, DBGSTOP_RECCR=0, DBGSTOP_LVD0=0, DBGSTOP_RPER=0, DBGSTOP_LVD2=0, DBGSTOP_CPER=0, DBGSTOP_WDT=0, DBGSTOP_LVD1=0
Debug Stop Control Register
| DBGSTOP_IWDT | Mask bit for IWDT reset/interrupt in the OCD run mode 0 (0): Enable IWDT reset/interrupt 1 (1): Mask IWDT reset/interrupt and stop IWDT counter |
| DBGSTOP_WDT | Mask bit for WDT reset/interrupt in the OCD run mode 0 (0): Enable WDT reset/interrupt 1 (1): Mask WDT reset/interrupt and stop WDT counter |
| DBGSTOP_LVD0 | Mask bit for LVD0 reset 0 (0): Enable LVD0 reset 1 (1): Mask LVD0 reset |
| DBGSTOP_LVD1 | Mask bit for LVD1 reset/interrupt 0 (0): Enable LVD1 reset/interrupt 1 (1): Mask LVD1 reset/interrupt |
| DBGSTOP_LVD2 | Mask bit for LVD2 reset/interrupt 0 (0): Enable LVD2 reset/interrupt 1 (1): Mask LVD2 reset/interrupt |
| DBGSTOP_RPER | Mask bit for SRAM parity error reset/interrupt 0 (0): Enable SRAM parity error reset/interrupt 1 (1): Mask SRAM parity error reset/interrupt |
| DBGSTOP_RECCR | Mask bit for SRAM ECC error reset/interrupt 0 (0): Enable SRAM ECC error reset/interrupt 1 (1): Mask SRAM ECC error reset/interrupt |
| DBGSTOP_CPER | Mask bit for Cache SRAM parity error reset/interrupt 0 (0): Enable Cache SRAM parity error reset/interrupt 1 (1): Mask Cache SRAM parity error reset/interrupt |